This a Full Time remote position working in Mexico with US clients.
We offer :
- 100% Remote work
- Salary in USD per hour
- Work 40 hours per week
Title : Design Verification Engineer
SystemVerilog / UVM expertise is mandatory.
At least 7 years of hands-on expertise.Strong grasp of digital logic design and verification methodologies.Experience verifying digital systems using standard IP components / interconnects (e.g., microprocessor cores, hierarchical memory subsystems). Proven ability to work autonomously and demonstrate technical confidence whenengaging with, and providing constructive feedback to, FE RTL design teams andCPU / IP micro-architects.Proficiency with industry-standard EDA simulation and debug tools.Solid abilities in debugging and root-cause analysis.Experience with scripting (Python, Perl).Excellent written and verbal communication skills in English are required.